PWMMR0S=DISABLED, PWMMR2R=DISABLED_, PWMMR5S=DISABLED, PWMMR6R=DISABLED_, PWMMR4S=DISABLED, PWMMR4I=DISABLED_, PWMMR2I=DISABLED_, PWMMR3R=DISABLED_, PWMMR6S=DISABLED, PWMMR5R=DISABLED_, PWMMR1R=DISABLED_, PWMMR6I=DISABLED_, PWMMR1I=DISABLED_, PWMMR3I=DISABLED_, PWMMR0R=DISABLED_, PWMMR4R=DISABLED_, PWMMR3S=DISABLED, PWMMR2S=DISABLED, PWMMR1S=DISABLED, PWMMR5I=DISABLED_, PWMMR0I=DISABLED_
Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs.
| PWMMR0I | Interrupt PWM0 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR0): Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC. |
| PWMMR0R | Reset PWM0 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR0_THE): Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. |
| PWMMR0S | Stop PWM0 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR0_THE_): Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. |
| PWMMR1I | Interrupt PWM1 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR1): Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. |
| PWMMR1R | Reset PWM1 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR1_THE): Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. |
| PWMMR1S | Stop PWM1 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR1_THE_): Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC. |
| PWMMR2I | Interrupt PWM0 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR2): Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC. |
| PWMMR2R | Reset PWM0 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR2_THE): Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. |
| PWMMR2S | Stop PWM0 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR2_THE_): Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. |
| PWMMR3I | Interrupt PWM3 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR3): Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC. |
| PWMMR3R | Reset PWM3 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR3_THE): Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. |
| PWMMR3S | Stop PWM0 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR3_THE_): Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC. |
| PWMMR4I | Interrupt PWM4 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR4): Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC. |
| PWMMR4R | Reset PWM4 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR4_THE): Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. |
| PWMMR4S | Stop PWM4 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR4_THE_): Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC. |
| PWMMR5I | Interrupt PWM5 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR5): Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC. |
| PWMMR5R | Reset PWM5 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR5_THE): Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. |
| PWMMR5S | Stop PWM5 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR5_THE_): Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC. |
| PWMMR6I | Interrupt PWM6 0 (DISABLED_): Disabled. 1 (INTERRUPT_ON_PWMMR6): Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC. |
| PWMMR6R | Reset PWM6 0 (DISABLED_): Disabled. 1 (RESET_ON_PWMMR6_THE): Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. |
| PWMMR6S | Stop PWM6 0 (DISABLED): Disabled 1 (STOP_ON_PWMMR6_THE_): Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |